PWMEN3=EM3, PWMEN1=EM1, PWMEN2=EM2, PWMEN0=EM0
PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0].
| PWMEN0 | PWM channel 0 enable 0 (EM0): CT32Bn_MAT0 is controlled by EM0. 1 (PWMMODE): PWM mode is enabled for CT32Bn_MAT0. |
| PWMEN1 | PWM channel 1 enable 0 (EM1): CT32Bn_MAT1 is controlled by EM1. 1 (PWMMODE.): PWM mode is enabled for CT32Bn_MAT1. |
| PWMEN2 | PWM channel 2 enable 0 (EM2): CT32Bn_MAT2 is controlled by EM2. 1 (PWMMODE): PWM mode is enabled for CT32Bn_MAT2. |
| PWMEN3 | PWM channel 3 enable Note: It is recommended to use match channel 3 to set the PWM cycle. 0 (EM3): CT32Bn_MAT3 is controlled by EM3. 1 (PPWMMODE): PWM mode is enabled for CT32Bn_MAT3. |
| RESERVED | Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined. |